將除法器修改成為乘法器

＊這次實作已經學習到如何將除法器修改成為乘法器＊

<1>.
將原本程式碼中while (r1 > 0)將原本的r1 > y改成r1 > 0

<2>.
r1 <= @(posedge sysclk)r1 - 1; 將原本r1-Y改成r1 - 1
r2 <= @(posedge sysclk) r2 + y;將原本r2-1改成r2 - y

<3>.
其中X與Y可修改成為自己想要的數字

pb= 0;
x = 5;
y = 8;
#250;
@(posedge sysclk);
for (x=5; x<=6; x = x+1)
----------------------------------------------------------------------------------
以下為程式完整內容:
`define NUM_STATE_BITS 2 `define IDLE 2'b00 `define INIT 2'b01 `define COMPUTE1 2'b10 `define COMPUTE2 2'b11 module cl(clk); parameter TIME_LIMIT = 110000; //1250; output clk; reg clk; initial clk = 0; always #50 clk = ~clk; always @(posedge clk) if ($time > TIME_LIMIT) #70 $stop;

endmodule

module slow_div_system(pb,ready,x,y,r2,sysclk);
input pb,x,y,sysclk;
output ready,r2;
wire pb;
wire [11:0] x,y;
reg ready;
reg [11:0] r1,r2;
reg [`NUM_STATE_BITS-1:0] present_state;

always
begin
@(posedge sysclk) enter_new_state(`IDLE);
r1 <= @(posedge sysclk) x; ready = 1; if (pb) begin @(posedge sysclk) enter_new_state(`INIT); r2 <= @(posedge sysclk) 0; while (r1 > 0) 將原本的r1 > y改成r1 > 0
begin
@(posedge sysclk) enter_new_state(`COMPUTE1);
r1 <= @(posedge sysclk) r1 - 1;將原本r1-Y改成r1 - 1
@(posedge sysclk) enter_new_state(`COMPUTE2);
r2 <= @(posedge sysclk) r2 + y;將原本r2-1改成r2-y

end
end
end
task enter_new_state;
input [`NUM_STATE_BITS-1:0] this_state;
begin
present_state = this_state;
#1 ready=0;
end
endtask

always @(posedge sysclk) #20
$display("%d r1=%d r2=%d pb=%b ready=%b", $time, r1,r2, pb, ready);
endmodule

module top;
reg pb;
reg [11:0] x,y;
wire [11:0] quotient;
wire ready;
integer s;
wire sysclk;

cl #20000 clock(sysclk);
slow_div_system slow_div_machine(pb,ready,x,y,quotient,sysclk);

initial
begin
pb= 0;
x = 6;
y = 8;
#250;
@(posedge sysclk);
for (x=6; x<=7; x = x+1)
begin
@(posedge sysclk);
pb = 1;
@(posedge sysclk);
pb = 0;
@(posedge sysclk);
wait(ready);
@(posedge sysclk);
if (x/y === quotient)
$display("ok");
else
$display("error x=%d y=%d x/y=%d quotient=%d",x,y,x*y,quotient);
end
$stop;
end
endmodule

首次研究

將程式中乘法改成除法

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